You can see 给你 that INT is just one of the many instructions (actually the Assembly Language representation (or should I say 'mnemonic') of it) that exists in the x86 instruction set. You can also find more information about this instruction in Intel's own manual found 给你.
PDF 摘要:
INT n/INTO/INT 3ーー呼叫中断程序
The INT n instruction generates a call to the interrupt or exception
用目标操作数指定的处理程序
operand specifies a vector from 0 to 255, encoded as an 8-bit unsigned
INTn 指令是
执行软件生成的对 interrupt handler 的调用。
正如你所看到的,0x80是你问题中的 目标操作数目标操作数。此时,CPU 知道它应该执行一些驻留在内核中的代码,但是什么代码呢?这是由 Linux 的中断向量决定的。
最有用的 DOS 软件中断之一是中断0x21。通过在寄存器中使用不同的参数(主要是 ah 和 al)调用它,您可以访问各种 IO 操作、字符串输出等等。
Linux 为 0x80设置了 interrupt handler,这样它就可以实现系统调用,这是用户界面程序与内核通信的一种方式。
.data
s:
.ascii "hello world\n"
len = . - s
.text
.global _start
_start:
movl $4, %eax /* write system call number */
movl $1, %ebx /* stdout */
movl $s, %ecx /* the data to print */
movl $len, %edx /* length of the buffer */
int $0x80
movl $1, %eax /* exit system call number */
movl $0, %ebx /* exit status */
int $0x80
编译并运行:
as -o main.o main.S
ld -o main.out main.o
./main.out
在受保护(32位)模式下,CPU 使用 IDT。IDT 是一个可变长度的结构,由 描述符(也称为门)组成,它告诉 CPU 有关中断处理程序的信息。这些描述符的结构比 IVT 的简单段偏移量条目要复杂得多,如下所示:
bytes 0, 1: Lower 16 bits of the ISR's address.
bytes 2, 3: A code segment selector (in the GDT/LDT)
byte 4: Zero.
byte 5: A type field consisting of several bitfields.
bit 0: P (Present): 0 for unused interrupts, 1 for used interrupts.*
bits 1, 2: DPL (Descriptor Privilege Level): The privilege level the descriptor (bytes 2, 3) must have.
bit 3: S (Storage Segment): Is 0 for interrupt and trap gates. Otherwise, is one.
bits 4, 5, 6, 7: GateType:
0101: 32 bit task gate
0110: 16-bit interrupt gate
0111: 16-bit trap gate
1110: 32-bit interrupt gate
1111: 32-bit trap gate
* IDT 可能是可变大小的,但是它必须是连续的,也就是说,如果您声明您的 IDT 是从0x00到0x50,那么您必须拥有从0x00到0x50的每个中断。操作系统不一定要使用所有的中断,所以现在位允许 CPU 正确地处理操作系统不打算处理的中断。
When an interrupt occurs (either by an external trigger (e.g. a hardware device) in an IRQ, or by the int instruction from a program), the CPU pushes EFLAGS, then CS, and then EIP. (These are automatically restored by iret, the interrupt return instruction.) The OS usually stores more information about the state of the machine, handles the interrupt, restores the machine state, and continues on.